Citation: | Chengbo Xue, Yougen Xu, Yue Hao, Wei Gao. Variation-Aware Task Mapping on Homogeneous Fault-Tolerant Multi-Core Network-on-Chips[J].JOURNAL OF BEIJING INSTITUTE OF TECHNOLOGY, 2019, 28(3): 497-509.doi:10.15918/j.jbit1004-0579.18057 |
[1] |
Zhang L, Han Y, Li H, et al. Fault tolerance mechanism in chip many-core processors[J]. Tsinghua Science & Technology, 2007, 12:169-174.
|
[2] |
Zhang L, Yu Y, Dong J, et al. Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors[C]//Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 2010:1566-1571.
|
[3] |
Srivastava A, Sylvester D, Blaauw D. Statistical analysis and optimization for VLSI:timing and power[M]. New York:Springer Science & Business Media, 2006.
|
[4] |
Sarangi S R, Greskamp B, Teodorescu R, et al. VARIUS:A model of process variation and resulting timing errors for microarchitects[J]. IEEE Transactions on Semiconductor Manufacturing, 2008, 21(1):3-13.
|
[5] |
Dick R P, Rhodes D L, Wolf W. TGFF:Task graphs for free[C]//Hardware/Software Codesign, 1998. Proceedings of the Sixth International Workshop on IEEE, 1998:97-101.
|
[6] |
Dick R. Embedded system synthesis benchmarks suites (E3S)[EB/OL]. http://ziyang.eecs.umich.edu/~dickrp/e3s/,2008.
|
[7] |
Huang W, Rajamani K, Stan M R, et al. Scaling with design constraints:Predicting the future of big chips[J]. IEEE Micro, 2011, 31(4):16-29.
|
[8] |
Sarangi S R, Greskamp B, Teodorescu R, et al. VARIUS:A model of process variation and resulting timing errors for microarchitects[J]. IEEE Transactions on Semiconductor Manufacturing, 2008, 21(1):3-13.
|
[9] |
Chang H, Sapatnekar S S. Prediction of leakage power under process uncertainties[J]. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2007, 12(2):1-27.
|
[10] |
Lei T, Kumar S. A two-step genetic algorithm for mapping task graphs to a network on chip architecture[C]//Euromicro Symposium on IEEE Digital System Design, 2003:180-187.
|
[11] |
Mirzoyan D, Akesson B, Goossens K. Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs[J]. ACM Transactions on Embedded Computing Systems (TECS), 2014, 13(2s):1-24.
|