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Article Navigation> JOURNAL OF BEIJING INSTITUTE OF TECHNOLOGY> 2016> 25(3): 403-412
JIANG Run-zhen, WANG Yong-qing, FENG Zhi-qiang, YU Xiu-li. Low complexity SEU mitigation technique for SRAM-based FPGAs[J]. JOURNAL OF BEIJING INSTITUTE OF TECHNOLOGY, 2016, 25(3): 403-412. doi: 10.15918/j.jbit1004-0579.201625.0314
Citation: JIANG Run-zhen, WANG Yong-qing, FENG Zhi-qiang, YU Xiu-li. Low complexity SEU mitigation technique for SRAM-based FPGAs[J].JOURNAL OF BEIJING INSTITUTE OF TECHNOLOGY, 2016, 25(3): 403-412.doi:10.15918/j.jbit1004-0579.201625.0314
shu

Low complexity SEU mitigation technique for SRAM-based FPGAs

doi:10.15918/j.jbit1004-0579.201625.0314
  • 1.

    School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China

  • 2.

    Beijing Institute of Astronautical Systems Engineering, Beijing 100076, China

  • Received Date:2014-12-28
    Abstract
  • An internal single event upset (SEU) mitigation technique is proposed, which reads back the configuration frames from the static random access memory (SRAM)-based field programmable gate array (FPGA) through an internal port and compares them with those stored in the radiation-hardened memory to detect and correct SEUs. Triple modular redundancy (TMR), which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it, is used to enhance the reliability. Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation, size and weight. The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect space-borne facilities from SEUs.
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    • References (17)
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