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Article Navigation> JOURNAL OF BEIJING INSTITUTE OF TECHNOLOGY> 2023> 32(1): 69-81
Ji Lai, Lixin Yang, Dejian Li, Chongfei Shen, Xi Feng, Jizeng Wei, Yu Liu. Design and Optimization of Winograd Convolution on Array Accelerator[J]. JOURNAL OF BEIJING INSTITUTE OF TECHNOLOGY, 2023, 32(1): 69-81. doi: 10.15918/j.jbit1004-0579.2022.094
Citation: Ji Lai, Lixin Yang, Dejian Li, Chongfei Shen, Xi Feng, Jizeng Wei, Yu Liu. Design and Optimization of Winograd Convolution on Array Accelerator[J].JOURNAL OF BEIJING INSTITUTE OF TECHNOLOGY, 2023, 32(1): 69-81.doi:10.15918/j.jbit1004-0579.2022.094
shu

Design and Optimization of Winograd Convolution on Array Accelerator

doi:10.15918/j.jbit1004-0579.2022.094
  • 1.

    School of Microelectronics, Tianjin University, Tianjin 300072, China

  • 2.

    Beijing Smart-Chip Microelectronics Technology Company Limited, Beijing 100192, China

  • 3.

    College of Intellegence and Computing, Tianjin University, Tianjin 300072, China

Funds:This paper was supported by the Project of the State Grid Corporation of China in 2022 (No. 5700-201941501A-0-0-00) and the National Natural Science Foundation of China (No. U21B2031).
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  • Author Bio:

    Ji Laireceived his B.Eng degree from the School of Microelectronics, Tianjin University, Tianjin, China, in 2020. He is currently pursuing a master’s degree in Tianjin University with the School of Microelectronics. His research interests include machine learning and optimization of software and hardware system design

    Lixin Yangreceived his M.B.A. degree from the School of Economics and Management, University of Chinese Academy of Sciences, Beijing, China. He is now an engineer in Beijing Smart-chip Microelectronics Technology Company Ltd. His research interests include main control chip design, embedded software design and application scheme design

    Dejian Lireceived his M.E. degree from Department of Electronic Engineering, Tsinghua University, Beijing, China. He is now an engineer in Beijing Smart-chip Microelectronics Technology Company Ltd. His research interests include VLSI design, master chip architecture design and low power circuit design

    Chongfei Shenreceived his M.E. degree from Department of Biomedical Engineering, Tsinghua University, Beijing, China. He is now an engineer in Beijing Smart-chip Microelectronics Technology Company Ltd. His research interests include industrial control chip architecture research, industrial high reliability software design and navigation algorithm research

    Xi Fengreceived his M.E. degree from Department of Microelectronics and Nanoelectronics, Tsinghua University, Beijing, China. He is now an engineer in Beijing Smart-chip Microelectronics Technology Company Ltd. His research interests include VLSI design, security chip architecture design and master chip architecture design

    Jizeng Weireceived the B.S. degree from the Harbin Institute of Technology, in 2004, and the M.S. and Ph.D. degrees in computer science from Tianjin University, Tianjin, China, in 2007 and 2010, respectively. He is currently an sssociate professor with the College of Intelligence and Computing, Tianjin University. His research interests include computer architecture, heterogeneous processor design, AI accelerator, and embedded systems

    Yu Liureceived his B.Eng in electronic engineering from Tianjin University, Tianjin, China, in 1998. From 1998 to 2000, he worked as an electronic engineer in Shenzhen, China. In 2000, he returned to Tianjin University and received his M.Eng in information and communication engineering and Ph.D. in signal and information processing both from Tianjin University in 2002 and 2005, respectively. Currently, he is a full professor with the School of Microelectronics, Tianjin University. From 2011 to 2012, Dr. Liu was a visiting research fellow with the Department of Electrical Engineering, Princeton University, Princeton, NJ, USA. His research interests include sensing and applications in multimedia signal processing, compressed sensing, and machine intelligence

  • Corresponding author:weijizeng@tju.edu.cn
  • Received Date:2022-08-31
  • Rev Recd Date:2022-10-29
  • Accepted Date:2022-11-08
  • Publish Date:2023-02-28
    Abstract
  • With the rapid development and popularization of artificial intelligence technology, convolutional neural network(CNN) is applied in many fields, and begins to replace most traditional algorithms and gradually deploys to terminal devices. However, the huge data movement and computational complexity of CNN bring huge power consumption and performance challenges to the hardware, which hinders the application of CNN in embedded devices such as smartphones and smart cars. This paper implements a convolutional neural network accelerator based on Winograd convolution algorithm on field-programmable gate array (FPGA). Firstly, a convolution kernel decomposition method for Winograd convolution is proposed. The convolution kernel larger than 3×3 is divided into multiple 3×3 convolution kernels for convolution operation, and the unsynchronized long convolution operation is processed. Then, we design Winograd convolution array and use configurable multiplier to flexibly realize multiplication for data with different accuracy. Experimental results on VGG16 and AlexNet network show that our accelerator has the most energy efficient and 101 times that of the CPU, 5.8 times that of the GPU. At the same time, it has higher energy efficiency than other convolutional neural network accelerators.
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