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CUI Wei, WU Si-liang. Small Area ROM Design for Embedded Applications[J]. JOURNAL OF BEIJING INSTITUTE OF TECHNOLOGY, 2007, 16(4): 460-464.
Citation: CUI Wei, WU Si-liang. Small Area ROM Design for Embedded Applications[J].JOURNAL OF BEIJING INSTITUTE OF TECHNOLOGY, 2007, 16(4): 460-464.
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Small Area ROM Design for Embedded Applications

  • School of Information Science and Technology, Beijing Institute of Technology, Beijing 100081, China

Funds:the National“863”Program Project (2006AA801302)
  • Received Date:2007-01-26
    Abstract
  • The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 pJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 μm 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, the layout design not only can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.
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    • References (14)
  • [1]
    Bertagnolli E,Hofmann F,Willer J,et al.ROS:An extremely hig h density mask ROM technolog y based on v ertical transistor cells[C] )1996 Symposium on V LSlT echnology Digest of T echnical P apers.Honolulu,Hi:IEEE,1996:58-59.
    [2]
    Yang B D,K im L S.A low pow er ROM using singlecharge sharing capacitor and hierarchical bit line[J] .IEEE T ransactio ns on V LSI Systems,2006,14(4):313-322.
    [3]
    Kaw ag ie H,T suji N.A low power char ge shar ing ROMusing dummy bit lines[C] )2003 International Symposium on Circuits and Systems.Piscataway,NJ:IEEE,2003:377-380.
    [4]
    Chang C R,Wang J S.Low power and high speed ROMmodules for A SIC applications[J] .IEEE Journal of Solid State Circuits,2001,36(10):1516-1523.
    [5]
    Yang B D,K im L S.A Lo w Pow er ROM using chargerecy cling and charg e sharing techniques[J] .IEEE Journal of Solid State Cir cuits,2003,38(4):641-653.
    [6]
    Chang C R,Wang J S.A new hig h speed/low power dynamic CMO S logic and its applicat ion to the design of anA OI type R OM[C] )I EEE International Symposium onCircuits and Systems.Orlando,FL:I EEE,1999:254-257.
    [7]
    M asuoka F.Reviews and prospects o f non volatile semiconducto r memories[J] .IEICE T r ansactions,1991,E74(4):868-874.
    [8]
    T akahashi H,Muramatsu S.A new contact programming ROM architectur e for dig ital signal processor[C] )IEEE Sy mposium on V LSI Circuits,Dig est of T echnicalPapers.Honolulu,Hi:IEEE,1998:58-161.
    [9]
    F an T,Chan K Y,Lu T C,et al.A new test structureand character ization methodology to identify ar ray leakagepath in M ask ROM[C] )2002 Int.Conference on M icroelectronic T est Structures.Piscataw ay,N J:IEEE,2002:45-48.
    [10]
    Cha H K,Yun I,Kim J et al.A 32 KB st andardCM O S antifuse one time progr ammable ROM embeddedin a 16 bit microcontroller[J] .IEEE Journal of SolidState Circuits,2006,41(9):2115-2124.
    [11]
    Sasag aw a R Fukushi I.Hig h speed cascode sensingscheme for 1 0 V co ntact progr amming mask ROM[C] )IEEE Symposium on VLSI Circuits,Digest of Technical Papers.Ho nolulu,Hi:I EEE,1999:95-96.
    [12]
    Nakamura H,M iyamoto J,Imamiya K,et al.A nov elsense amplifier for flex ible voltage operation NA ND flashmemor ies[C] )IEEE Symposium on V LSI Circuits,Digest of T echnical Papers.Honolulu,Hi:IEEE,1995:71-72.
    [13]
    Khellah M M.Elmasr y M I.L ow power design ofhigh capacitive CM OS circuits using a new charge sharing scheme[C] )IEEE Int.Solid State Cir cuits Conference,Digest o f T echnical Papers.Honolulu,Hi:IEEE,1999:286-287.
    [14]
    Yang B D,K im L S.A low power charge recyclingROM architecture[C] )IEEE Symposium on Circuitsand Systems.Piscataw ay,NJ:IEEE,2001:510-513.
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